The memory access time of a processor can be reduced by using cache memory, which is generally smaller and faster than main system memory. A cache hit occurs if a memory location that is needed by the processor is found in the cache. The probability of a cache hit can be increased by storing the most recently accessed data in the cache, and by increasing the cache size. However, cache access time typically also increases with cache size. Because of this trade-off, many processors use multi-level caches. In a two-level cache, for example, the level-one (L1) cache can be both substantially smaller and faster than the level-two (L2) cache. This minimizes the cache access time for the most recently accessed data, while also maintaining an access time faster than main system memory access for a substantial amount of recently accessed data.
Multi-level cache systems may be strictly exclusive, substantially exclusive, non-exclusive, or strictly inclusive. In a strictly exclusive multi-level cache system, data must reside in at most one of the L1 and L2 caches. In a substantially exclusive multi-level cache system, data resides in at most one of the L1 and L2 caches under common operating conditions. In a non-exclusive multi-level cache system, data may reside in either or both of the L1 and L2 caches. In a strictly inclusive multi-level cache system, all data in the L1 cache must also reside in the L2 cache. In the remainder of this specification, multi-level cache systems that may be strictly exclusive or substantially exclusive are referred to as exclusive multi-level cache systems.
The selection of a type of multi-level cache system involves design trade-offs. An exclusive multi-level cache system can store more data than a non-exclusive or strictly inclusive cache system, which increases the probability of a cache hit. However, exclusive multi-level cache systems can also be more complex, which under some conditions may increase associated processing overhead.
Multi-level cache systems commonly operate in a single exclusivity mode, which may be strictly exclusive, substantially exclusive, non-exclusive, or strictly inclusive. However, depending on the task to be performed, an exclusive multi-level cache system may have better average memory access time than a non-exclusive or strictly inclusive multi-level cache system, or vice versa. In addition, though an L2 cache may be capable of operating in an exclusive, a non-exclusive, or a strictly inclusive multi-level cache system, processors are generally more restricted. There are some processors that work with only non-exclusive or strictly inclusive multi-level cache systems, and other processors that work with only exclusive multi-level cache systems. Moreover, an L2 cache may have similar restrictions to those just described for processors. In view of the foregoing, it would be desirable to provide a technique to enable one or more processors to control a multi-level cache system so that the multi-level cache system can operate in different exclusivity modes, and to enable one or more processors to recognize the exclusivity capabilities of an L2 cache.